| 摘要 |
PURPOSE:To simplify the software processing procedure, and to shorten the data transfer time by advancing simultaneously a DMA read cycle and a DMA write cycle by a multiple bus controller, and executing instantaneously a control of an up-bus and a down-bus, in order to execute simultaneously an information exchange of two systems by a multiple bus generator. CONSTITUTION:By a control bus sequential converter 14, one DMA cycle is brought to a time division and a data, a read mode and a write mode are generated simultaneously in the course of one cycle, and a multiple bus controller 15 outputs a DMA data latch signal (p) and a DMA write gate signal (q) for executing a bus control by two directions of an up-bus R and a down-bus S, to a multiple bus generator 16. n the multiple bus generator 16, a data which is outputted from a communication memory is inputted onto the up-bus R and the down-bus S by DMA data latch signal (p) which is outputted from the multiple bus controller 15, in order to transfer simultaneously a data of a communication memory A9 and a data of a memory B23, to the communication memory B23, and the memory A9, respectively.
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