Improved memory control for a scanning CRT visual display system

摘要

A scanning CRT graphics video display system is disclosed in which a graphics display controller reads formatted information signals into a refresh memory in a read-modify-wire mode and reads the stored information out of the refresh memory in a display mode. During the display mode the information in the memory is provided on a common data bus for sequential reading into four different shift registers having different bit capacities with the different bit capacities effectively implementing predetermined delays such that the shift registers will properly simultaneously read out the information that was sequentially loaded into the shift registers. A programmable logic sequencer provides address select signals in addition to address signals provided by the graphics display controller so as to address four different memory planes in the refresh memory, and the address select signals are also utilized to sequentially enable the loading of the four shift registers. The logic sequencer provides a clock timing signal to the controller for controlling the frequency of operation thereof. During the display mode the clock frequency is provided at a first frequency while during the read-modify-write mode, which occurs during video blanking, the sequencer provides a substantially higher frequency clock signal to the controller to implement rapid reading of information into the refresh memory.