发明名称 |
Equalized biased array for proms and eproms. |
摘要 |
<p>An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage VBIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage VT above VBIAS. Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage VT above VBIAS. The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting. </p> |
申请公布号 |
EP0225442(A2) |
申请公布日期 |
1987.06.16 |
申请号 |
EP19860112824 |
申请日期 |
1986.09.17 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
KASZUBINSKI, JEFFREY K.;WILMOTH, DAVID D.;COFFMAN, TIMMIE M.;SCHRECK, JOHN F. |
分类号 |
H03K5/00;G11C16/06;G11C16/24;G11C17/00;G11C17/18;(IPC1-7):G11C17/00 |
主分类号 |
H03K5/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|