发明名称 HOLD TIME MONITOR CIRCUIT
摘要 PURPOSE:To prevent a main processor from being in the hold state for a long time to break down a system by monitoring the hold time of the main processor by a timer which generates a time-up signal after a prescribed time. CONSTITUTION:A timer means 103 discriminates the hold start of a main processor 101 in accordance with the output of AND between a hold request signal from a subprocessor 102 to the main processor 101 and a hold response signal, which is outputted from the main processor 101 to the subprocessor 102 in response to the hold request signal, to start measuring the hold time, and the time-up signal is generated and is supplied to a reset signal generating means 104 when a prescribed hole monitor time elapses. The reset signal generating means 104 resets the subprocessor, which issues the hold request signal, on a basis of this time-up signal.
申请公布号 JPS62131347(A) 申请公布日期 1987.06.13
申请号 JP19850272799 申请日期 1985.12.04
申请人 FUJI ELECTRIC CO LTD 发明人 OSAWA CHIHARU
分类号 G06F11/30;G06F11/16;G06F13/20;G06F13/36;G06F15/16 主分类号 G06F11/30
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