| 摘要 |
<p>PURPOSE:To process a signal efficiently at high speed by making the power consumption of a specific output buffer larger than other output buffers and increasing driving capacity. CONSTITUTION:An ECL gate array is constituted of an internal cell 1 organizing an arbitrary logic circuit in the gate array, input or output buffers 2 having comparatively small power consumption, various power generating circuits 3 and output buffers 4 flowing currents until element performance is lead out sufficiently and having large power consumption. When using the ECL gate array, the output buffers 4 having large power consumption are employed in a signal at high speed controlling a system. Since output impedance is sufficiently low to heavy load in the output buffer 4, driving capacity does not run short. Because one or two signal pins are required for particularly processing a signal at high speed normally, the output buffers 4 having two large driving capacity are arranged at location being point-symmetric with regard to the center of a chip.</p> |
