| 摘要 |
PURPOSE:To grasp properly error state information by displaying the error state information immediately by the hardware only when an NMi error is generated. CONSTITUTION:If an NMi error takes place in a processor 172, the error state information is stored in an error register 182. When the processor 172 is selected by a selector switch on an operation panel, a CPUSL2 signal is sent, a gate circuit 192 is opened and the content of the error register 182 is given to an error information bus 20. A ROM 25 decodes a data on the error information bus to generate a display data and outputs it. A multiplexer 26 uses a HDERR signal sent from the processor 172 to select a path (a) into a path (b). Thus, the display data generated in the ROM 25 drives a display section 24 via the path (b) of the multiplexer 26 and the error state is displayed in alphanumerics of O-F.
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