| 摘要 |
<p>PURPOSE:To increase the number of series stages of a MOS transistor constituting a ROM cell while maintaining high speed properties, by providing a discharging path discharging fast the input potential of a data latch circuit. CONSTITUTION:The inverse of precharge signal PRE is set at an L level and an address Add is changed. Thus MOS transistors Tr2 and Tr3 are turned on with a Tr1 turned off respectively. Then nodes N1 and N2 are precharged by a power supply VDD and MOSTr11-1n of a ROM cell 11 are all turned on by the output of an address decoder 12. Thus the potential of the node N1 is discharged. When this potential is reduced less than a reference level Vref, the output of a comparator 17 is set at an H level. When a MOSTr4 is turned on to discharge the potential of the node N2 via a MOSTr5. Thus it is possible to maintain the fast operation of a semiconductor storage device regardless of the number of series stages of a ROM cell.</p> |
