| 摘要 |
<p>PURPOSE:To normally read data of a ROM even when the scale of a circuit became large and delay occurred due to influences of load possessed by wiring that transmits control signals by operating a ring counter by reading signals from outside and reading data. CONSTITUTION:A memory cell 3 writes only 2 bits of data possessed by an address line selected by an address decoder 2. A data latch 4 and an output buffer 5 write the 2 bits data received. A controlling section 6 includes a ring counter consisting of D flip-flops 14-17 operated by fall of a clock inputted to a phi terminal. When address data Ao-An are inputted to an address input buffer 1, an address in which data to be read out to the address decoder 2 are stored is decoded. After data of the address are outputted from the memory cell 3, the data are stored in the data latch 4, and then, data read out by the output buffer 5 are outputted to a block of next stage.</p> |
