| 摘要 |
PURPOSE:To make a dynamic logic circuit higher in speed, by providing a level shifting transistor to be used for accumulating electric charges at a voltage which is lower than the voltage, at which a supply voltage or logic level becomes a high level 'H' against the floating capacity of a transistor group. CONSTITUTION:During a precharge period when a clock phi is '0', a pMOS transistor (Tr) 1 is conducted and electric charges are accumulated in the gate capacities of nMOS Trs16 and 17 constituting a buffer gate 5 at a voltage VDD and, furthermore, electric charges are accumulated in the floating capacity of a logic gate combined circuit 3 at a voltage which is lower than the voltage VDD by the threshold voltage of an nMOS Tr 2. During a sampling period when the clock phi is '1', an nMOS Tr 4 is conducted and the input voltage of the buffer gate 5 is fixed in accordance with the logical values of input logic signals A-E, and then, a logic output signal (A.B+C+D.E) is obtained at an output terminal 18. The discharge performed when the output signal is '1' is quickly performed. |
