发明名称 TRANSMITTER-RECEIVER OF DIGITAL DATA
摘要 PURPOSE:To miniaturize an error correcting circuit used for two-way communication, by using the parity bit producing circuit of an error correction encoding circuit as the syndrome producing circuit of an error correction decoding circuit also. CONSTITUTION:At the time of reception, a reception mode instruction is given from the output port 20 of a CPU to a control circuit 21 and a switch 26 is set to the (a) side. Seven-bit serial data 34 are successively loaded into a syndrome register 23 and data register 25 simultaneously. Corrected data 35 are outputted as output signals 36 through the switch 26. At the time of transmission, a transmission instruction is outputted from the output port 20 of the CPU and all circuits are switched to an encoding circuit. Four-bit parallel information 33 to be encoded is loaded into a parallel/serial conversion circuit 22. Upon completing the loading, the serial data 34 are supplied to the data register 25 and syndrome register 23.
申请公布号 JPS62116019(A) 申请公布日期 1987.05.27
申请号 JP19850254862 申请日期 1985.11.15
申请人 NIPPON HOSO KYOKAI <NHK> 发明人 YAMADA TSUKASA;YANAGIMACHI AKIO;ISOBE TADASHI
分类号 H04L1/00;H03M13/00 主分类号 H04L1/00
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