| 摘要 |
PURPOSE:To obtain a high on/off ratio characteristic by inputting an output of an FET inputting a signal and switched to an FET gate of the next stage thereby eliminating the effect of the on-resistance and reducing the signal leakage at switch-off. CONSTITUTION:When a clock control voltage VC supplied to a control terminal 3 is at a high level, the FET Q10 is turned on and the FET Q 11 is turned off and an input signal VIN is sent to a gate of the FET Q12 via the FET Q10. In this case, the FET Q13 is turned on and the FET Q12 and a resistor 16 constitute a common source circuit and the said signal is outputted as an output voltage Vout. Since the FET Q12 shows a high impedance, a linear output with less effect in the dependency of the on-resistance of the input level to the FET Q10 is obtained. In bringing the control voltage VC to a low level, the FET Q10, Q13 are turned off, the FET Q11 is turned on and the circuit shows the off-function. Further, the source side of the FET Q12 is interrupted from a power supply VSS. Since the signal leakage caused via a parasitic capacitance is leaked through more number of stages than a conventional switch by one stage, a signal appearing at an output is decreased.
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