| 摘要 |
PURPOSE:To know the phase of a defect faithfully and to obtain a correct flaw inspection signal by finding the peak value of the flaw inspection signal at every cycle within a set phase. CONSTITUTION:The clock from a basic clock circuit 50 is demultiplexed by a frequency divider 100 and converted into a sine wave by an oscillator 110 to excite a probe 10 through a power amplifier 120. The flaw detection signal from the probe 10 is amplified selectively by an amplifier 130 and a tuned amplifier 140 and then inputted to a 0-cross circuit 150. A phase setter 160 calculates the upper and lower limit phase values phi1 and phi2 based upon the phase of the peak value of the flaw inspection signal obtained from a standard defect material and inputs them to a CPU 180. The CPU 180 inputs the outputs of the basic clock circuit 50, frequency dividers 100, 0-cross circuit 150, A/D converter 170, and phase setter 160 respectively to find the peak value of the flaw inspection signal at every cycle within the set phase, and compares it with the last peak value to judge whether there is a maximum peak value in each cycle or not, so that when there is the maximum value, it is displayed externally as a flaw signal.
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