| 摘要 |
<p>A phase-frequency discriminator comprising a first RS latch coupled to provide first output signals, said first RS latch including an S input terminal coupled to receive first input signals; a second RS latch coupled to provide second output signals, said second RS latch including an S input terminal coupled to receive second input signals; a third RS latch including an S input terminal coupled to a Q^¨B7 output terminal of said first RS latch and including a Q^¨B7 output terminal couples to an R input terminal of said first RS latch and including a Q^¨B7 output terminal coupled to an R input terminal of said first RS latch; a fourth RS latch including an S input terminal coupled to a Q^¨B7 output terminal of said second RS latch and including a Q^¨B7 output terminal coupled to an R input terminal of said second RS latch; and reset means for providing a reset signal when said first and second input signals both have changed from a first to a second logical state such that the first and second output signals change back from the second to the first logical state after a reset time interval substantially long enough for the respective first and second output signals to reach full logic amplitude levels for the second logical state.</p> |
