| 摘要 |
PURPOSE:To evade such a case where the synchronous timing signal is producd by mistake if the input data has a drop-out part or the noises are superposed on the input data, by using a clock generator, a shift register, a dividing counter and a data discordance detecting circuit. CONSTITUTION:The input data of each bit is sampled by a clock signal in a 1/n cycle and shifted successively to each stage of a shift register 2. Here if the input data has a drop-out part or contains noises, the data is coincident with either of those stages. In such a case, a dividing counter 3 is never reset to avoid such a case where the counter 3 produces he synchronous timing signal by the wring timing due to the noises, etc. Then it is possible to secure the synchronization between the dividing action of the counter 3 and the normal input data only in case the sample values are coincident with each other between the stages of the first half and those of the second half. |
