| 摘要 |
PURPOSE:To improve greatly the processing capacity of a general-purpose register by selecting one of (p) columns through a column selecting circuit and then the data on plural m-bit registers independently among (nXm) bits through plural row selecting circuits and delivering those selected column and data to plural data buses respectively. CONSTITUTION:It is supposed that a column selection signal 2-6 is already active by a register set selecting signal 1-10 and 64 bits in the longitudinal direction of the 1st register column 2-4 are selected. Then a control gate 2-7 selects the data of total 64 bits of the register column 2-4 equivalent to eight 8-bit registers as long as the 1st reading signal 2-9 or the 2nd reading signal 2-10 is active. Then the 1st and 2nd register selecting circuits 2-13 and 2-16 select the data delivered onto the 1st and 2nd data buses 1-5 and 1-6 by the same timing and delivered again onto both buses 1-5 and 1-6 via an input/output buffer 2-14 and an output driver 2-17. |
