发明名称 TIMING SYNCHRONIZING SYSTEM
摘要 PURPOSE:To suppress jitters by controlling the phase of a sampling pulse of an A-D converter continuously. CONSTITUTION:The A-D converter 1 digitizes a reception signal, a timing extraction circuit 2 extracts a timing signal from the reception signal and a vector conversion circuit 3 converts the scaler quantity into the vector quantity. Then a low-pass filter 4 removes high-frequency components and an APC circuit 7 changes the phase of a sampling frequency analogically, that is, continuously depending on the phase of the input vector to control a voltage controlled oscillator 8. Then the output clock of the voltage-controlled oscillator 8 samples the A-D converter.
申请公布号 JPS62108643(A) 申请公布日期 1987.05.19
申请号 JP19850248268 申请日期 1985.11.06
申请人 FUJITSU LTD 发明人 KAKO TAKASHI
分类号 H04L27/22;H04L7/00;H04L7/033 主分类号 H04L27/22
代理机构 代理人
主权项
地址