发明名称 INTERNAL CIRCUIT STRUCTURE FOR LSI
摘要 PURPOSE:To reduce the capacity without lowering the function, by using one register in common by plural inputs and outputs. CONSTITUTION:A register 4 is a common register of input/output buffers 2, 3, and in which input/output buffer a data is stored is determined by a data selector 5. In this way, the number of gates can be curtailed by 5-10 gates per 1 bit. Also, a through-path which does not pass through the register 4 is provided, and a selector 6 is provided on the post-stage of the register (not shown in the figure), by which even against that which requires a simultaneity of 16 bits in an external equipment of a 16-bit access of an input/output buffer side, read-out and write can be executed by an access timing of a CPU itself.
申请公布号 JPS62107318(A) 申请公布日期 1987.05.18
申请号 JP19850247003 申请日期 1985.11.06
申请人 HITACHI LTD 发明人 KIMURA HIROYUKI;KASAHARA TOSHIRO;OSHIGA TAKAYUKI;FUJIWARA KATSUHIRO
分类号 G06F3/00;G06F5/06;G06F5/16 主分类号 G06F3/00
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