| 摘要 |
PURPOSE:To obtain a memory which has no problem of the address setup time, by taking the external write signal into the inside with synchronization via the internal clock generated through the logic change of the address input in an internal synchronous memory. CONSTITUTION:The internal clock generating circuit G detects the logic change of the address inputs A0-An through the delay circuit and the exclusive OR circuit and then generates the internal clock CE. The control signal generating circuit G1 receives the clock CE and then generates successively and with a delay the control signals CE1-CE4 to control the address buffer circuit B, address decoder circuit DE, memory cell array C and input/output buffer circuit IO each. In this case, the internal write signal W delivers the reverse-phase signal of the external write signal through the AND circuit A with the synchronization secured by the control signal CE2 of the address decoder circuit DE. |
