A multiphase frequency selective phase locked loop with multiphase sinusoidal and digital outputs.

摘要

A circuit for providing a multiphase digitally synthesized sinusoidal output signal (A',B',C') having a predetermined phase relationship to a multiphase source signal (A,B,C). The circuit comprises a phase comparator (12, 14, 16, 22), a voltage controlled oscillator (30) and a synthesizer (34). The voltage controlled oscillator produces an output frequency representative of the phase error. The variable frequency output is used for shifting the phase of the synthesized output signal in response to the phase error output signal of the phase comparator. The synthesizer digitally synthesizes at a predetermined amplitude the multiphase sinusoidal output signal. In an alternate embodiment, a second synthesizer is provided for producing a second multiphase synthesized output signal.