| 摘要 |
<p>PURPOSE:To attain a reading action at a high speed by accelerating the switching action between non-selection and selection modes and then decelerating the switching action between the selection and non-selection modes respectively to secure a multiple selection period of a data line. CONSTITUTION:The output signal of a NOR gate circuit G1 is delayed by the 1st delay circuit. The output signal of an inverter circuit N5 serving as an output circuit of the 1st delay circuit is supplied to the input terminal at one side of a NOR gate circuit G2 and a NAND gate circuit G3 respectively. While the output signal of the circuit N5 is delayed further by the 2nd delay circuit. The output signal of an inverter circuit N9 serving as an output circuit of the 2nd delay circuit is supplied to the input terminal at the other side of both circuits G2 and G3 respectively. The total delay time of the 1st and 2nd delay circuits is set at the value equivalent to the timing approximately synchronous with the selecting action of a word line. The internal complement address signals ayi and the inverse of ayi are supplied to a Y decoding circuit YDCR consisting of a NAND gate.</p> |
