| 发明名称 |
Digital signal processor |
| 摘要 |
Data which are read from a memory area (1) are fed to an arithmetic calculation area (3), so that a specified arithmetic activity is applied to the data. The arithmetic calculation area (3) has a pipeline multiplier (310), so that the input data are multiplied at high speed. <IMAGE>
|
| 申请公布号 |
DE3636095(A1) |
申请公布日期 |
1987.04.23 |
| 申请号 |
DE19863636095 |
申请日期 |
1986.10.23 |
| 申请人 |
MITSUBISHI DENKI K.K. |
发明人 |
ANDO,HIDEKI;NAKAYA,MASAO;MACHIDA,HIROHISA |
| 分类号 |
G06F17/10;G06F7/52;G06F7/544;G06F17/16;(IPC1-7):G06F7/52 |
主分类号 |
G06F17/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
