发明名称 Semiconductor memory device including an improved data refreshing arrangement and a system employing the same
摘要 The dynamic RAM has a refresh circuit with two operation modes. In the first operation mode, a variety of signals necessary for the refresh operation are formed in the dynamic RAM. Accordingly, the refresh operation of the dynamic RAM is performed completely automatically. As long as the refresh operation is being carried out, a busy signal is produced from the dynamic RAM to prevent an erroneous writing operation or reading operation. In the second operation mode, the refresh operation of the dynamic RAM is performed in synchronism with a starting signal supplied from an external unit. The busy signal produced by the dynamic RAM that is working under the first operation mode can be used as a starting signal for the dynamic RAM that is working under the second operation mode. Therefore, the refresh operation is effected in synchronism for the dynamic RAM's that constitute the memory system, and the through-put of the memory system is enhanced.
申请公布号 US4660180(A) 申请公布日期 1987.04.21
申请号 US19840658910 申请日期 1984.10.09
申请人 HITACHI, LTD. 发明人 TANIMURA, NOBUYOSHI;KAWAMOTO, HIROSHI
分类号 G11C11/403;G11C11/406;(IPC1-7):G11C7/00;G11C8/00 主分类号 G11C11/403
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