| 摘要 |
PCT No. PCT/JP84/00280 Sec. 371 Date Jan. 16, 1985 Sec. 102(e) Date Jan. 16, 1985 PCT Filed Jun. 1, 1984 PCT Pub. No. WO84/04984 PCT Pub. Date Dec. 20, 1984.According to this invention, there are provided a plurality of memories in which predetermined data are written and a plurality of gates. Parity check bits are grouped into a plurality of groups in response to the bit number of the addresses of the memories. Of the grouped parity checkbits, the parity checkbits corresponding to the addresses of the memories are supplied to the addresses and the outputs of the memories are supplied to the gates so as to decode the parity check bits, whereby a threshold value is identified on the basis of the outputs of the gates.
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