发明名称 PHASE SYNCHRONIZING SYSTEM
摘要 <p>PURPOSE:To prevent occurrence of twice reading and slip in elastic store by making phase relation of read reset pulse of an elastic store and read reset pulse maximum distance at the time of initial setting. CONSTITUTION:The system consists of a frame synchronizing circuit, a WR, WI forming counter, an elastic store, a comparator circuit, an RR forming counter, an RI forming counter and an OR gate. The WR, WI forming counter makes initial setting of WR by frame pulse Ff at the time of establishment of frame synchronism from the frame synchronizing circuit basing on clock WCK extracted from a transmission line, and thereafter, pulses are outputted repeatedly at every necessary frequency. In this case, relative phase of periodical pulse WR that designates the head of writing and periodical pulse RR that designates the head of reading is set to make RR positioned at nearly the central time position of adjoining two WR at the time of returning of frame synchronism.</p>
申请公布号 JPS6286933(A) 申请公布日期 1987.04.21
申请号 JP19850225999 申请日期 1985.10.12
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 UEDA HIROMI;KAINO MASATERU;TOKIZAWA IKUO
分类号 H04J3/06;H04L7/00 主分类号 H04J3/06
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