| 摘要 |
PURPOSE:To shorten a test time by allowing a counter which counts a clock signal to hold an output signal which is set to logic '1' and loading it in the counter. CONSTITUTION:A counter testing circuit is provided with FFs 4 (40-43) as a holding means and also provided with a delay circuit 2 and a gate 3 as a loading means. Output signals (q) (q0-q3) of low-order (i) digits of the counter 1 are all set to logic '1' after (i) clock signals CK are inputted to the counter 1, so a clock signal CK consisting of pulses as many as the number of the digits of the counter 1 is only inputted to verify the counting function of the counter 1, thereby shortening its required test time. |
