发明名称 ARITHMETIC CONTROLLER
摘要 <p>PURPOSE:To reduce the number of steps in a program by arbitrarily setting an arithmetic iteration range and the number of iteration loops so as to control an address when an iteration is applied to input data at plural points. CONSTITUTION:In an address generation control means 30, a register file 1 inputs the count value of a register file counter 2, and transmits the number of loops which are initialized and previously stored based on the count value. Loop registers 3-1-3-4 temporarily store the number of loops of the register 1. Loop number counters 4-1-4-4 are installed on the registers 3-1-3-4, respectively, and an order control decoder 6 controls the order of these registers and counters according to the order instruction from a program memory 7. On the other hand, an address generator circuit 11 outputs an address signal based on the control instruction from the means 30. With this constitution, the arithmetic iteration range and the number of iteration loops can be optically set so as to control an address, thereby shortening the processing time.</p>
申请公布号 JPS6273377(A) 申请公布日期 1987.04.04
申请号 JP19850212102 申请日期 1985.09.27
申请人 TOSHIBA CORP 发明人 SUZUKI KAORU
分类号 G06F9/32;G06F17/10;G06F17/14 主分类号 G06F9/32
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