| 摘要 |
PURPOSE:To form by means of the self alignment method a MESFET of the offset gate structure having a large withstand voltage between the gate and the drain and a fine size by forming an insulating film in the side portions of the recessed pattern of the gate electrode so that said insulating film is thinner in the source side than in the drain side. CONSTITUTION:An active layer 2 and an insulating film 3 are formed on a GaAs substrate 1, and a gate electrode pattern 4 is formed of a recessed pattern. Then, a second insulating film 5 is formed on the whole surface of the first insulating film 3 and the gate electrode pattern 4. At this time, if the flow of the reaction gas in the CVD method is made in the direction parallel with the semiconductor substrate 1 and from the direction perpendicular to the gate direction, the deposition condition of a silicon nitride film in the gate electrode pattern 4 becomes thinner in the upstream portion of the gas and thicker in the downstream portion of the gas. Then, the insulating film 5 is etched to expose the n-type active layer 2 in the lower portion of the gate electrode pattern 4, and a gate electrode 7 is formed. Subsequently, this is covered with photoresist except for the FET portion, the first insulating film 3 is selectively removed while leaving the second insulting film 6 on the side portions of the gate electrode pattern, and an ohmic electrode 8 is formed. |
