发明名称 SEQUENCE LOGICAL UNIT
摘要 PURPOSE:To form a controller with the simple hardware with no intervention of the software by adding a deciding means to the controller to decide the logical value of each bit according to a logic tree. CONSTITUTION:A controller 1 is connected to a ROM2 via an external address bus 4 and an external data bus 5 and delivers the state designating information which is decided unconditionally to the input information 101. While the information 102 sets the state of a controlled system (not shown in figure). A memory 3 holds the present state of the relevant system and delivers it as a past history as a storage circuit. The output of the memory 3 is fed back again as the information 101 on the controller 1 and use for decision of the information 12. Thus the correspondence is secured between the address storing the state designating information and the lowest position of a logic tree for logical value of each bit. As a result, the controller 1 can be formed with the hardware with no intervention of the software.
申请公布号 JPS6265102(A) 申请公布日期 1987.03.24
申请号 JP19850203811 申请日期 1985.09.13
申请人 NEC CORP 发明人 YAMASHITA MIKIO
分类号 G05B19/02;G06F7/00;G06F17/30 主分类号 G05B19/02
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