| 摘要 |
PURPOSE:To test top divide on function block units and utilize a logic simulation pattern formed at logic designing time by providing a probe PAD capable of observing a signal level of wiring between function blocks in a wiring region between the function blocks. CONSTITUTION:In a large-scale integrated circuit in which function blocks are separately logically designed, disposing wirings are executed with function block wiring regions 1-4 of the size necessary for laying the blocks, and the blocks and I/O cell region 5 are then wired therebetween by a wiring region 6 between the blocks, probe PADs 7 capable of observing a signal level of wirings between the blocks are provided in the regions 1-4. In case of a circuit test, the PADs 7 can observe the output of a test pattern by the probes without limit in the number of the I/OPADs 8 of input/output terminals at the observing points. Thus, tests can be separately executed per the block unit. |
