发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PURPOSE:To obtain the titled device having a strong resistance to variance on a manufacturing process and to the mixing of a noise and to attain high speed read out by supplying the output of a signal inverting circuit to the gate of a load transistor and dropping the action voltage supplied to the signal inverting circuit. CONSTITUTION:Between a transistor 17 of an inverter 19 in a bias circuit 20 and a Vcc, an I-type MOS transistor 71 is inserted, further, between the Vcc and a Vss in the bias circuit 20, the section between the source and the drain of two I-type MOS transistors 72 and 73 is serially inserted, and the gate of the two transistors 72 and 73 is connected to the Vcc. The serial connecting point of two transistors 72 and 73 is connected to the gate of the above- mentioned transistor 1. Namely, transistors 71, 72 and 73 constitute the voltage dropping circuit to drop an electric power source voltage Vcc and supply to the inverter 19, and in the same way, even at a bias circuit 25, the voltage dropping circuit composed of transistors 74, 75 and 76 is provided.</p>
申请公布号 JPS6258496(A) 申请公布日期 1987.03.14
申请号 JP19850198937 申请日期 1985.09.09
申请人 TOSHIBA CORP;TOSHIBA MICRO COMPUT ENG CORP 发明人 ASANO MASAMICHI;IWAHASHI HIROSHI;IMAI MIZUHO
分类号 G11C17/00;G11C16/06 主分类号 G11C17/00
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