MICROWORD GENERATION MECHANISM UTILIZING SEPARATE PROGRAMMABLE LOGIC ARRAYS

摘要

The microword generation mechanism includes a first cycle programmable logic array (40) responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction, a second cycle programmable logic array (41) responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction, and at least one additional programmable logic array (42, 43) responsive to the processor instruction to be executed for providing the remainder of the microwords needed to perform the effective address calculations for the operands of the instruction, to fetch the operands from the main storage unit and to execute the operations called for by the instruction.