| 摘要 |
PURPOSE:To form a high-withstanding-voltage output stage and a high-speed small signal circuit on one chip pnd to reduce the area of elements with respect to the withstanding voltage and a driving current, by forming a CMOS transistor in a two-well mode, and providing an embedded layer, whose conducting type is the same as VG layers at a drain taking out port of a DMOS transistor. CONSTITUTION:On the surface of a P<-> type silicon substrate 31, low concentration N<-> type epitaxial layers (VG layers) 33a and 33b are provided through first and second high-concentration impurity layers 32a and 32b. A two-well type CMOS transistor is provided at one VG layer 33a. On the surface of the other VG layer 33b, a DMOS transistor is provided so that a part of a drain region covers the surface of the substrate 31. A drain contact region (N<+> layer) 53 of the transistor is provided at an N-type impurity layer 42 (for withstanding voltage correction between the substrate and the drain), whose conducting type is the same as that of the VG layer 33b. Thus, a semiconductor integrated circuit, in which a high speed logic element and the high-withstanding-voltage high power DMOS are incorporated, can be formed within a small element area in comparison with a conventional circuit. |
