| 摘要 |
<p>A clock signal generating circuit for a dynamic type semiconductor memory device including an input voltage level control unit (1) for converting a transistor-transistor-logic (TTL) drive level to a metal-oxide-semiconductor (MOS) drive level during transmission of an address strobe signal; an address buffer control unit (2) for generating an address signal and an inverted address signal in response to a trailing edge of the address strobe signal, a clock signal generating unit (4) for generating a clock signal used for a word line selection and an input signal for a next stage in response to a low level of the address strobe signal, and an inhibiting unit (11, 12) for inhibiting a drive of the word line by the clock signal when the address strobe signal is at high level at the timing of a leading edge of the clock signal. The inhibiting unit prevents erroneous operation of the memory device from being caused by noise in the address strobe signal.</p> |
