| 摘要 |
A CMOS inverter circuit wherein the input device is formed with a p-well as the back-gate and is adapted to receive negative going input signals at the p-well. The gate of the input device is connected to a bias supply set just above the threshold for the input device. With the input signal voltage at 0, the inverter is on, and the output voltage is near 0. As the input signal voltage goes negative, the threshold of the input device increases due to the back-gate bias effect, and it turns off, causing the output voltage to go positive.
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