发明名称 ERROR PROCESSING SYSTEM
摘要 PURPOSE:To avoid an error correction failure by turning ON a modifying bit with respect to data concerned in a buffer memory when a bit error is corrected and moved in the error memory. CONSTITUTION:The move -in data MID transmitted from a main memory MEM is checked whether it has an bit error or not by an error checking circuit CHK. If it has the error, the error-corrected data by the correcting circuit CRCT is selected and outputted. As a signal FOUND is at a level L, the output of a selector SL4 turns out to be a read data RD to an access request source REQ through gates G2 and G3. With the conventional techniques, conditions turning ON the demodified bit M of a memory TAG at the time of moving in only covers the case of a write request, however, said bit M can be turned ON when the the operation detects a bit error in a read request mode.
申请公布号 JPS6246358(A) 申请公布日期 1987.02.28
申请号 JP19850185091 申请日期 1985.08.23
申请人 FUJITSU LTD 发明人 TATEISHI TERUTAKA
分类号 G06F11/10;G06F11/00;G06F12/08;G06F12/16 主分类号 G06F11/10
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