Arithmetic logic unit.

摘要

An arithmetic logic circuit comprising a plurality of cells of conventional logic circuits for performing logical and arithmetic operations in combination with a kill circuit in each one of said cells which is responsive to bits of first and second operands T and B. a clock signal Ø1*, a propagate bit P and a carry-in bit C<Sub>in</Sub> for selectively providing a carry-out bit C<Sub>out</Sub> and/
or a carry-bypass circuit coupled to each one of a plurality of sets of said cells which is responsive to propagate bits P from said cells in each set, a clock signalØ<Sub>2</Sub>* and a carry-in bit C<Sub>in</Sub> for allowing said carry-in bit C<Sub>in</Sub> to bypass selected ones of said cells.