| 摘要 |
PURPOSE:To decide surely the frequency of an input signal by changing the frequency dividing ratio with a count in response to the relation of phase between the output signal and input signal of a variable frequency divider. CONSTITUTION:The phase of an output signal A' of a slice circuit 10 and the output signal D of a variable frequency divider 26 is compared by a phase comparator 11 to form a delay pulse phi1 and a lead pulse phip, which are fed to a U/D counter 12. When a data storage device 17 stores the delay signal phi1, the signal d1 of logic H is outputted and when the lead signal phip is stored, a storage device 18 outputs the signal dp of logic H and the output signals d1, dp are logic L in other case. The frequency dividing ratio of the variable frequency divider 26 is set to 187 when the output signal d1 of the data storage device 17 is logic H and set 262 when the output signal dp of the device 18 is logic H and set to 192 when both the outputs are logical L respectively, and the frequency dividing ratio of the variable frequency divider 26 is changed sequentially, then the output signal D of the variable frequency divider 26 is locked to the frequency of the received line supervisory signal. |
