| 发明名称 |
MULTILEVEL CONTROLLER FOR A CACHE MEMORY INTERFACE IN A MULTIPROCESSING SYSTEM |
| 摘要 |
<p>MULTMULTILEVEL CONTROLLER FOR A CACHE MEMORY INTERFACE IN A MULTIPROCESSING SYSTEM OF TIRE INVENTION A two level controller has been described for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities.</p> |
| 申请公布号 |
CA1218162(A) |
申请公布日期 |
1987.02.17 |
| 申请号 |
CA19840451184 |
申请日期 |
1984.04.03 |
| 申请人 |
BURROUGHS CORPORATION (DELAWARE) |
发明人 |
STECKLER, THOMAS M. |
| 分类号 |
G06F15/16;G06F9/28;G06F12/08;(IPC1-7):G06F12/02;G06F9/22 |
主分类号 |
G06F15/16 |
| 代理机构 |
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代理人 |
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| 主权项 |
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