| 摘要 |
PURPOSE:To decrease power consumption, by a constitution; wherein a voltage is simultaneously applied to a second polycrystalline silicon layer, which is formed on a polycrystalline silicon layer that is connected between word lines and a power source, and a well beneath a first polycrystalline silicon layer; and the resistance of the first polycrystalline silicon layer is increased by the application of the voltage. CONSTITUTION:When information is written in a memory cell M, a low level voltage is applied to an N-type well 2 and a second polycrystalline silicon layer 7. Therefore a first polycrystalline silicon layer 5 is kept at a relatively low resistance value. A specified voltage Vpp is applied to a selected word line WL, and the writing is executed as in a conventional device. At the time of reading, a specified voltage is applied to the N-type well 2 and the second polycrystalline silicon layer 7 through contact parts 2a and 7a. A depletion layer is expanded between the surface facing the lower N-type well 2 and the surface facing the upper second polycrystalline silicon layer 7 in the first polycrystalline silicon layer 5, and a very high resistance value is obtained. Therefore,the resistance value of an element Q1a in the word line WL, which is not selected, becomes large, and the power consumption can be decreased. |
