| 摘要 |
<p>Sets of coefficients have to be fed in close succession and in an alternating manner from one of two RAM memories (RA, RB) to a transmission component (U) for digital signals, for example a level selector, comprising a channel processor (KP). The sets of coefficients coming from a processor, (P) which can be controlled by an adjusting element, arrive in alternation at the RAM memory which precisely is not delivering its memorized data to the channel processor (KP). In the event of fast transmission of the coefficients, the obstacle is that the latter have to be stored in the RAM memories under disseminated addresses. A transmission circuit (AR, DR, S1 to S8), in which the RAM addresses and coefficients are stored in an intermediate memory in parallel under the same continual addresses supplied by an address generator (AG), ensures rapid transmission of the coefficients.</p> |
