发明名称 PARALLEL PROCESSING TYPE PROCESSOR
摘要 <p>PURPOSE:To facilitate a processing between frames or fields of a picture signal or that between frames and fields of the picture signal and to make it possible to use the elements of low power consumption by delaying a signal by means of a delay circuit and processing. CONSTITUTION:A high definition TV signal of a TV set with 1,125 pieces of scanning lines and with n-pieces of samples for one scanning line, is spread in four phases of A-D in order to lower the sampling frequency to 1/4. The delayed-line number of frame memories are allocated by 281X(n) to memories 41-43 and by 282X(n) to a memory 44 to make a one-frame delay. In this case, the sequence of the picture elements inputted to phases A, B, C, and D is in the order A-phase, B-phase, C-phase, and D-phase on the unit of scaning line. Taking the example of the A-phase, the inputting is done in every fifth scanning line in a manner that the first through n-th picture elements of a line 1,123 are inputted, then 4 lines are jumped and the first through n-th picture elements of a line 2 are inputted, and further, the first through n-th ones of a line 1,122, then jumping by 4 lines, the first through n-th ones of a line 1 are inputted.</p>
申请公布号 JPS6232579(A) 申请公布日期 1987.02.12
申请号 JP19850172874 申请日期 1985.08.06
申请人 FUJITSU LTD 发明人 OKAZAKI TAKESHI;MATSUDA KIICHI;TSUDA TOSHITAKA
分类号 H02P6/16;G06T1/20;G06T9/00;H02P6/20;H03M9/00 主分类号 H02P6/16
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