发明名称
摘要 PURPOSE:To deal with an abrupt shift in phase by controlling the variable frequency dividing circuit of an internal reference signal generating means while giving warning once a variable delay means reaches a minimum or maximum set value, and thus varying a reference signal and returning the operation point of the variable delay means to the center. CONSTITUTION:A digital signal from an input terminal 1 is delayed through a variable delay circuit 6 by a value set in initialization, and then outputted to an output terminal 2. A synchronizing signal detecting circuit 13 detects a synchronizing signal to output pulses at equal intervals when no phase shift is found. The output of a quartz oscillator 3, on the other hand, is frequency-divided by a variable frequency divider 4, and a phase difference detecting circuit 8 detects the phase shift between the circuits 4 and 13 to control a variable delay circuit 5, thereby correcting their phase shift. This correction is performed at the set period of a timer circuit 7 and a phase monitoring circuit 10 monitors the phase difference; when a preset phase difference is detected, a phase difference detecting circuit 9 detects the phase difference in output between the circuit 5 and synchronous detecting circuit 12. Then, the circuits 4 and 6 are controlled through a control circuit 14 to deal with an abrupt phase shift.
申请公布号 JPS626374(B2) 申请公布日期 1987.02.10
申请号 JP19810166897 申请日期 1981.10.19
申请人 NIPPON ELECTRIC CO 发明人 FURUKAWA TERUTOSHI;TAKAHASHI BUNJI
分类号 H04L1/06;H04B7/26;H04H20/67;H04H40/18;H04L7/033 主分类号 H04L1/06
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