发明名称 MEMORY READ SYSTEM
摘要 <p>PURPOSE:To prevent erroneous read due to an electric noise without reducing the bit density by reading information from the same cell plural times continuously and comparing these information to determine output information. CONSTITUTION:Information read to a node N1 is taken into a latch circuit 1 by a control clock phi1 and is latched. Information is read again from the same cell, and read information is latched in a latch circuit 2 by a control clock phi2, and information read from the same cell is latched in a latch circuit 3 by a control clock phi3 similarly. Three pieces of latched information are subjected to majority decision by a majority decision circuit 4, and the result is read out to the external through an output buffer 5. The majority decision circuit 4 consists of 3 AND circuits A1-A3 and one OR circuit OR and outputs the same information as information inputted to the majority of the first - third input terminals.</p>
申请公布号 JPS6224498(A) 申请公布日期 1987.02.02
申请号 JP19850162100 申请日期 1985.07.24
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 BABA TATSUO
分类号 G11C17/00;G11C29/00 主分类号 G11C17/00
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