| 摘要 |
PURPOSE:To prevent simultaneous turning-on of a P-FET and an N-FET of a CMOS tristate output buffer by using the first logic circuit where driving MOSFETs in the reference potential side are connected in series and the second logic circuit where they are connected in parallel. CONSTITUTION:A P-FET Q14 and an N-FET Q13 constitute the CMOS tristate output buffer. A logic circuit G1 (G2) to which an output control signal oe (or the signal, the inverse of oe) and an internal signal D are inputted drives the FET Q14 (or Q15) through an inverter IV1 (or IV2). FETs Q1 and Q2 in the reference potential side are connected in parallel in the circuit G1, and FETs Q5 and Q6 in the earth side are connected in series in the circuit G2. Since a threshold voltage VL2 of the FET Q5 is higher than a threshold voltage VL1 of the FET Q1 by the substrate effect or the like, FETs Q13 and Q14 are prevented from being turned on simultaneously when the internal siganl D is changed, and the noise due to a through current is prevented. |
