发明名称 DELAY CIRCUIT
摘要 PURPOSE:To constitute a delay circuit which delays a pulse by a long time with a high accuracy in a minute step by providing two oscillating means slightly different in oscillation frequency and counter means which count output pulses of these oscillating means. CONSTITUTION:The first counter circuit 5 counts output pulses of the first ring oscillator consisting of means 4, 6, and 7 and outputs one pulse when the counted value reaches a designated value, and a signal GATE1 is zero hereafter to stop oscillation. The second ring oscillator consisting of means 4a, 6a, and 7a and the second counter circuit 5a are operated similarly. Designated counted values for the first and the second counter circuits 5 and 5a are set to (m) and (n) respectively and m+n=C is made true, and (n) is changed with a control computer 10 to obtain a pulse E, which is obtained by delaying an input pulse A by the period difference between two ring oscillators, in an output terminal 9.
申请公布号 JPS6220414(A) 申请公布日期 1987.01.29
申请号 JP19850159842 申请日期 1985.07.19
申请人 FUJITSU LTD 发明人 OZAKI KAZUYUKI;GOTO YOSHIAKI;OKUBO KAZUO;ITO AKIO;ISHIZUKA TOSHIHIRO
分类号 H03K5/135 主分类号 H03K5/135
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