发明名称 DIGITAL PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To suppress a jitter component while keeping the following capacity to the low frequency component of input data by providing a low pass filter used for correction due to a correction coefficient of a coefficient multiplier and performing correction by the output of this filter also. CONSTITUTION:The output of a low pass filter 7 is added to the output of a coefficient multiplier 3. Correction by the output of the filter 7 is equivalent to the practical change of a coefficient K due to the change of input data. Thus, the coefficient concerning intervals calculated by input data is increased with respect to the low frequency component of input data, and the coefficient concerning a phase position Pi is increased with respect to the high frequency component like jitter. When data is fetched into the filter 7, the variation of the low frequency component due to wow and flutter or the like is equalized approximately in a one-clock period.
申请公布号 JPS6220442(A) 申请公布日期 1987.01.29
申请号 JP19850158038 申请日期 1985.07.19
申请人 KENWOOD CORP 发明人 ODAKA KAZUO;TAKAHASHI TETSUO
分类号 G11B20/14;H03L7/06;H04L7/02;H04L7/033 主分类号 G11B20/14
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