| 摘要 |
PURPOSE:To attain an access to the block of data where the bit log2n of an address changed by using a selection memory, a memory of 2n columns and a bidirectional multiplexer which arranges the data on the memory of 2n columns on 8n pieces of data bus. CONSTITUTION:The memory 17 of 2n columns is designated by the output data of a selection memory 22 which uses the bits 0 - log2n of an address bus 12 and the data size selection signal 9 as the address inputs. The designated data of maximum (n) bytes are arranged on an 8n-bit data bus by multiplexers 18-21 which are controlled by the output of a decoder 15 which uses the data size selection signal as an input. Thus a single access is possible with different data lengths up to a long word to a block of data where the bit log2n of the address changes. This attains a high-speed access. |
