| 摘要 |
<p>In a master-slave type flip-flop circuit including a normal function in a normal mode for flip/flop operation and a scanning function in a scanning mode for testing an integrated circuit, the master-slave type flip-flop circuit comprises : a master stage having a first pair of differential transistors (Q₁₅, Q₁₆) for taking in data, a second pair of differential transistors (Q₁₃, Q₁₄) for latching data taken in to the first pair of differential transistors, a third pair of differential transistors (Q₄₃, Q₄₄) for taking in scanning data, and a fourth pair of differential transistors (Q₄₁, Q₄₂) for activating the second and third pairs of differential transistors in the scanning mode; and a slave stage having a first pair of differential transistors (Q₂₅, Q₂₆) for taking in data from the master stage, a second pair of differential transistors (Q₂₃, Q₂₄) for latching data taken in to the first pair of differential transistors, a third pair of differential transistors (Q₅₃, Q₅₄) for latching scanning data, and a fourth pair of differential transistors (Q₅₁, Q₅₂) for activating the first and third pairs of differential transistors in the scanning mode. </p> |
