Phase-locked loop frequency synthesizer.

摘要

In an improved phase-locked loop frequency synthesizer, an voltage are continuously applied from a power source to a fixed divider and a programmable divider respectively composed of such lower electric power consuming means as C-MOS circuit such that the fixed and programmable dividers preserve the counting value thereof when the inputs are interrupted to be applied to the fixed and programmable dividers at the time of changing from an phase-locked loop to an open loop so that phase lock is achieved in a short time with less consumption of electric power.