发明名称 |
Self-timed precharge circuit |
摘要 |
A self-timed precharge circuit for a memory array consisting of an X-line complement circuit connected to the outputs of a plurality of falling edge detectors, and a precharge generator circuit connected to the output of the X-line complement circuit. Each falling edge detector is connected to a separate wordline (WL, WL+1, . . . WL+N) of the system memory array. In operation, the precharge generator circuit is triggered with a signal on the output lead from a falling edge detector which is activated when the selected wordline (WL, WL+1, . . . WL+N) connected thereto resets.
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申请公布号 |
US4638462(A) |
申请公布日期 |
1987.01.20 |
申请号 |
US19850696624 |
申请日期 |
1985.01.31 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
RAJEEVAKUMAR, THEKKEMADATHIL V.;TERMAN, LEWIS M. |
分类号 |
G11C11/407;G11C7/12;G11C7/22;G11C8/08;G11C8/18;G11C11/409;G11C11/41;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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